PAC-Designer 5.2

PAC-Designer is a complete design and verification solution supporting platform management, power management and programmable clock device families.
PAC-Designer has fully integrated design and simulation environment for Platform Manager, Power Manager II, and ispClock devices.

Main Features :
- Fully integrated design and simulation environment for Platform Manager, Power Manager II, and ispClock devices
- High level logic design mechanism
- Easy-to-use GUI
- For Platform Manager it works in conjuction with ispLEVER to form a complete CPLD/FPGA design environment
- Works with other Lattice software support tools such as IP Express
- Hierarchical design entry
- High level design entry for flexible power management
- Design utilities